Faculty Members

LANGUAGE ≫ Japanese
liao-wang-1.jpg

Assistant Professor
LIAO Wang

Doctor (Informatics), Osaka University, Japan, 2019

Areas of specialization VLSI
FPGA
Quantuam Error Correction
Laboratory/research office Quantum and Classical Integrated Circuit Laboratory
Integrated circuits (ICs) consist of numerous basic cells for computation; they are the core components of computers, which serve as the brains of the Information Society. To support response to the explosively increasing demands for computation tasks in applications such as artificial intelligence (AI), our laboratory is mainly working toward the development of methods for the design of high-efficiency, high-reliability classical ICs. Furthermore, in anticipation of the promising　quantum computing in the era of post-CMOS, we are researching methods for meeting challenges related to the integration of quantum bits, including quantum error correction, so as to realize practical large-scale quantum computers.
Current research topics soft error Accelerator based on FPGA for Deep Learning Fault Tolerant Quantum Computing
Educational background 2019: Doctor, Osaka University, Japan
2015: Master, Northeastern University (P.R.C), China
2013: Bachelor, Shenyang University of Technology, China
Professional background 2023-: Visiting Researcher, the University of Tokyo
2023-: Assistant Professor, Kochi University of Technology
2022-2023: Visiting Researcher, NTT Computer and Data Science Laboratories
2021-2023: Project-specific Researcher, University of Tokyo
2019-2021: Research Associate, Kochi University of Technology
2019-2021: Visiting Researcher, Osaka University
Licenses
Academic societies IEEE

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Courses

* Courses provided in English are shown with (E) mark

Undergraduate school
  • CAD/Descriptive Geometry
  • Introduction to Computer Engineering
  • Experiments of Electronic and Photonic 2
Graduate school

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Research activities

Research papers
  1. Authors: Yasunari Suzuki, Yosuke Ueno, LIAO Wang, Masamitsu Tanaka, Teruo Tanimoto
    Title: Circuit designs for practical-scale fault-tolerant quantum computing
    Journal: IEEE Symposium on VLSI Technology and Circuits, IEEE
    Year: 2023
  2. Authors: Shin-Ichiro Abe, Masanori Hashimoto, LIAO Wang, Takashi Kato, Hiroaki Asai, Kenichi Shimbo, Hideya Matsuyama, Tatsuhiko Sato, Kazutoshi Kobayashi, Yukinobu Watanabe
    Title: A Terrestrial SER Estimation Methodology based on Simulation coupled with One-Time Neutron Irradiation Testing
    Journal: IEEE Transactions on Nuclear Science, Vol. 70, No. 8, pp. 1652-1657, IEEE
    Year: 2023
  3. Authors: LIAO Wang, Suzuki Yasunari, Tanimoto Teruo, Ueno Yosuke, Tokunaga Yuuki
    Title: WIT-Greedy: Hardware System Design of Weighted ITerative Greedy Decoder for Surface Code
    Journal: ASP-DAC
    Year: 2023
  4. Authors: Suzuki Yasunari, Sugiyama Takanori, Arai Tomochika, LIAO Wang, Inoue Koji, Tanimoto Teruo
    Title: Q3DE: A Fault-Tolerant Quantum Computer Architecture for Multi-bit Burst Errors by Cosmic Rays
    Journal: IEEE MICRO
    Year: 2022
  5. Authors: Tanaka Tomonari, LIAO Wang, Hashimoto Masanori, Yukio Mitsuyama
    Title: Impact of Neutron-Induced SEU in FPGA CRAM on Image-Based Lane Tracking for Autonomous Driving: From Bit Upset to SEFI and Erroneous Behavior
    Journal: IEEE Transactions on Nuclear Science , Vol. 69, No. 1
    Year: 2022
  6. Authors: LIAO Wang, Ito Kojiro, Abe Shin-ichiro, Mitsuyama Yukio, Hashimoto Masanori
    Title: Characterizing Energetic Dependence of Low-Energy Neutron-induced SEU and MCU and Its Influence on Estimation of Terrestrial SER in 65-nm Bulk SRAM
    Journal: IEEE Transactions on Nuclear Science, Vol. 68, No. 6
    Year: 2021
  7. Authors: LIAO Wang, Hashimoto Masanori, Manabe Seiya, Watanabe Yukinobu, Abe Shin-ichiro, Tampo Motonobu, Takeshita Soshi, Miyake Yasuhiro
    Title: Impact of the Angle of Incidence on Negative Muon-induced SEU Cross Sections of 65-nm Bulk and FDSOI SRAMs
    Journal: IEEE Transactions on Nuclear Science, Vol. 67, No. 7
    Year: 2020
  8. Authors: LIAO Wang, Hashimoto Masanori, Manabe Seiya, Abe Shin-ichiro, Watanabe Yukinobu
    Title: Similarity Analysis on Neutron and Negative Muon-induced MCUs in 65-nm Bulk SRAM
    Journal: IEEE Transactions on Nuclear Science, Vol. 66, No. 8
    Year: 2019
  9. Authors: LIAO Wang, Hashimoto Masanori
    Title: Analyzing Impacts of SRAM, FF and Combinational Circuit on Chip-level Neutron-induced Soft Error Rate
    Journal: IEICE Transactions on Electronics, Vol. E102C, No. 4
    Year: 2019
  10. Authors: LIAO Wang, Hashimoto Masanori, Manabe Seiya, Watanabe Yukinobu, Abe Shin-ichiro, et al.
    Title: Measurement and Mechanism Investigation of Negative and Positive Muon-induced Upsets in 65-nm Bulk SRAMs
    Journal: IEEE Transactions on Nuclear Science, Vol. 65, No. 8
    Year: 2018
Invited lectures
  1. Test flow for soft error-induced malfunction in FPGA-based autonomous driving system using virtual environment, 2022
  2. Reliability Evaluation of Soft Error in SRAM FPGA-based Lane Edge Tracking in Autonomous Driving System, Soft Error Symposium, online, 2021
  3. Characterization of 65-nm Bulk SRAM Using Muon, Spallation and Quasi-monoenergetic Neutron Sources, Soft Error Symposium, Fukuoka, 2018
Awards
  1. IEEE CAS Kansai Chapter Student Research Award, 2020
  2. RADECS 2018 Best Paper Reward, 2018
Grants-in-Aid for Scientific Research from the Japanese government
  1. Project title: Protection Strategies for Configuration Information of SRAM-based FPGA against Soft Errors at Advanced Process Node for Space Applications
    Category: Grant-in-Aid for Early-Career Scientists
    Project number: 21K17721
    Project period: 2021-2023
    Total budget amount: 4,550,000 yen
    Keywords:

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Social activities

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