Research papers |
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Authors: Tomonari Tanaka, Wang Liao, Masanori Hashimoto, Yukio Mitsuyama
Title: Impact of Neutron-induced SEU in FPGA CRAM on Image-based Lane Tracking for Autonomous Driving: from Bit Upset to SEFI and Erroneous Behavior
Journal: IEEE Transactions on Nuclear Science, Vol. 69, No. 1, pp. 35-42
Year: 2022
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Authors: Wang Liao, Kojiro Ito, Masanori Hashimoto, Yukio Mitsuyama
Title: Characterizing Energetic Dependence of Low-energy Neutron-induced SEU and MCU and Its Influence on Estimation of Terrestrial SER in 65 nm Bulk SRAM
Journal: IEEE Transactions on Nuclear Science, Vol. 68, No. 6, pp. 1228-1234
Year: 2021
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Authors: Yukio Mitsuyama, Takashi Asada, Makio Eguchi
Title: Measurement of Variations in FPGAs under Various Load Conditions
Journal: IPSJ Transaction on System LSI Design Methodology, Vol. 13
Year: 2020
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Authors: Hiroyuki Ochi, Kosei Yamaguchi, Tetsuaki Fujimoto, Munshi Hotate, Takashi Kishimoto, Toshiba Higashi, Takashi Imagawa, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Wataru Takahashi, Kazutoshi Wakabayashi, Hideyoshi Onodera, Yukio Mitsuyama, Jaehoon Yu, Masanori Hashimoto
Title: Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture with Overlay Via-Switch Crossbars
Journal: IEEE Transactions on VLSI Systems,, Vol. 26, No. 12, pp. 2723-2736
Year: 2018
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Authors: H. Hihara, A. Iwasaki, M. Hashimoto, H. Ochi, Y. Mitsuyama, H. Onodera, H. Kanbara, K. Wakabayashi, T. Sugibayashi, T. Takenaka, H. Hada, M. Tada, M. Miyamura, T. Sakamoto
Title: Sensor Signal Processing Using High-Level Synthesis with a Layered Architecture
Journal: IEEE Embedded Systems Letters
Year: 2018
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Authors: H. Konoura, D. Alnajjar, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, K. Wakabayashi, M. Hashimoto, T. Onoye, H. Onodera
Title: Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-based Design and Its Irradiation Testing
Journal: lEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E97-A, No. 12, pp. 2518-2529
Year: 2014
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Authors: R. Harada, Y. Mitsuyama, M. Hashimoto, T. Onoye
Title: Set Pulse-Width Measurement Suppressing Pulse-Width Modulation and Within-Die Process Variation Effects
Journal: lEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E97-A, No. 7, pp. 1461-1467
Year: 2014
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Authors: H. Konoura, T. Kameda, Y. Mitsuyama, M. Hashimoto, T. Onoye
Title: NBTI Mitigation Method by Inputting Random Scan-In Vectors in Standby Time
Journal: lEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E97-A, No. 7, pp. 1483-1491
Year: 2014
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Authors: H. Konoura, T. Imagawa, Y. Mitsuyama, M. Hashimoto, T. Onoye
Title: Comparative Evaluation of Lifetime Enhancement with Fault Avoidance on Dynamically Reconfigurable Devices
Journal: lEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E97-A, No. 7, pp. 1468 -1482
Year: 2014
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Authors: T. Kameda, H. Konoura, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, M. Hashimoto
Title: Field Slack Assessment for Predictive Fault Avoidance on Coarse-Grained Reconfigurable Devices
Journal: IEICE Transactions on Information and Systems, Vol. E96-D, No. 8, pp. 1624-1631
Year: 2013
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Authors: T. Amaki, M. Hashimoto, Y. Mitsuyama, T. Onoye
Title: A Worst-Case-Aware Design Methodology for Noise-Tolerant Oscillator-Based True Random Number Generator with Stochastic Behavior Modeling
Journal: IEEE Transactions on Information Forensics and Security, Vol. 8, No. 8, pp. 1331-1342
Year: 2013
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Authors: D. Alnajjar, Y. Mitsuyama, M. Hashimoto, T. Onoye
Title: Pvt-Induced Timing Error Detection Through Replica Circuits and Time Redundancy in Reconfigurable Devices
Journal: IEICE Electronics Express (ELEX), Vol. 10, No. 5
Year: 2013
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Authors: R. Harada, Y. Mitsuyama, M. Hashimoto, T. Onoye
Title: Impact of NBTI-Induced Pulse-Width Modulation on Set Pulse-Width Measurement
Journal: IEEE Transactions on Nuclear Science
Year: 2013
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Authors: D. Alnajjar, H. Konoura, Y. Ko, Y. Mitsuyama, M. Hashimoto, T. Onoye
Title: Implementing Flexible Reliability in a Coarse-grained Reconfigurable Architecture
Journal: IEEE Transactions on VLSI Systems
Year: 2012
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Authors: H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
Title: Adaptive Performance Compensation with In-Situ Timing Error Predictive Sensors for Subthreshold Circuits
Journal: IEEE Transactions on VLSI Systems, Vol. 20, No. 2, pp. 333-343
Year: 2012
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Authors: H. Konoura, Y. Mitsuyama, M. Hashimoto, T. Onoye
Title: Stress Probability Computation for Estimating NBTI-Induced Delay Degradation
Journal: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E94-A, No. 12, pp. 2545-2553
Year: 2011
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Authors: H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
Title: Neutron-Induced Soft Errors and Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM
Journal: IEEE Transactions on Nuclear Science, Vol. 58, No. 4, pp. 2097-2102
Year: 2011
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Authors: R. Harada, Y. Mitsuyama, M. Hashimoto, T. Onoye
Title: Measurement Circuits for Acquiring Set Pulse Width Distribution with Sub-Fo1-Inverter-Delay Resolution
Journal: lEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E93-A, No. 12, pp. 2417-2423
Year: 2010
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Authors: H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
Title: Transistor Variability Modeling and its Validation With Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits
Journal: lEEE Transactions on VLSl Systems, Vol. 18, No. 7, pp. 1118-1129
Year: 2010
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Authors: H. Fuketa, M. Hashimoto, Y. Mitsuyama, T.Onoye
Title: Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction
Journal: IEICE Trans on Fundamentals of Electronics, Communications and Computer Science, Vol. E92-A, No. 12, pp. 3094-3102
Year: 2009
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Authors: K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
Title: An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability
Journal: IEICE Transactions on Electronics, Vol. E92-C, No. 2, pp. 281-285
Year: 2009
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Authors: Y. Mitsuyama, K. Takahashi, R. Imai, M. Hashimoto, T. Onoye, I. Shirakawa
Title: Area-Efficient Reconfigurable Architecture for Media Processing
Journal: IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E91-A, No. 12, pp. 3651-3662
Year: 2008
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Authors: Y. Mitsuyama, M. Kimura, T. Onoye, I. Shirakawa
Title: Architecture of IEEE802.11i Cipher Algorithms for Embedded Systems
Journal: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E88-A, No. 4, pp. 899-906
Year: 2005
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Authors: Z. Andales, Y. Mitsuyama, T. Onoye, I. Shirakawa
Title: A Novel Dynamically Reconfigurable Hardware-based Cipher
Journal: 情報処理学会論文誌, Vol. 42, No. 4, pp. 958-966
Year: 2001
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