Faculty Members

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Associate Professor
MITSUYAMA, Yukio

Doctor of Information Science and Technology, Osaka University, Japan, 2010

  • Gender: Male
  • Affiliation:
    - School of Systems Engineering
    - Electronic and Photonic Systems Engineering Course, Department of Engineering, Graduate School of Enginering
  • Personal web site: http://www.sceng.kochi-tech.ac.jp/mituyama/
Areas of specialization System LSI Design
Reconfigurable Architecture
FPGA Application Design
VLSI Design Methodology
Laboratory/research office Integrated Systems Laboratory
To support the development of novel information processing systems, we are doing research to develop a reconfigurable architecture design for system LSI, a method for the design of reconfigurable system LSI, and applications for implementation in reconfigurable systems.
Current reseach topics
Educational background 2000: Master, Osaka University, Japan
1998: Bachelor, Osaka University, Japan
Professional background 2013-2014: Visiting Researcher, University of California, Irvine
2009-2011: Part-time Lecturer, College of Science and Engineering, Ritsumeikan University
2007-2011: Assistant Professor, Graduate School of Engineering, Osaka University
2002-2007: Assistant Professor, Graduate School of Engineering, Osaka University
Licenses
Academic societies The Institute of Electronics, Information and Communication Engineers (IEICE)
IEEE
Information Processing Society of Japan (IPSJ)
The Institute of Image Electronics Engineers of Japan (IIEEJ)

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Courses

* Courses provided in English are shown with (E) mark

Undergraduate school
  • Graduation Thesis
  • Principles of Electric Circuits
  • Logic Circuit
  • Information Science 1
  • Experiments in System Engineering
  • Experiments of Electronic and Photonic 1
Graduate school
  • Individual Work for Graduate

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Research activities

Research papers
  1. Authors: H. Hihara, A. Iwasaki, M. Hashimoto, H. Ochi, Y. Mitsuyama, H. Onodera, H. Kanbara, K. Wakabayashi, T. Sugibayashi, T. Takenaka, H. Hada, M. Tada, M. Miyamura, T. Sakamoto
    Title: Sensor Signal Processing Using High-Level Synthesis with a Layered Architecture
    Journal: IEEE Embedded Systems Letters
    Year: 2018
  2. Authors: H. Konoura, D. Alnajjar, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, K. Wakabayashi, M. Hashimoto, T. Onoye, H. Onodera
    Title: Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-based Design and Its Irradiation Testing
    Journal: lEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E97-A, No. 12, pp. 2518-2529
    Year: 2014
  3. Authors: H. Konoura, T. Kameda, Y. Mitsuyama, M. Hashimoto, T. Onoye
    Title: NBTI Mitigation Method by Inputting Random Scan-In Vectors in Standby Time
    Journal: lEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E97-A, No. 7, pp. 1483-1491
    Year: 2014
  4. Authors: H. Konoura, T. Imagawa, Y. Mitsuyama, M. Hashimoto, T. Onoye
    Title: Comparative Evaluation of Lifetime Enhancement with Fault Avoidance on Dynamically Reconfigurable Devices
    Journal: lEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E97-A, No. 7, pp. 1468 -1482
    Year: 2014
  5. Authors: R. Harada, Y. Mitsuyama, M. Hashimoto, T. Onoye
    Title: Set Pulse-Width Measurement Suppressing Pulse-Width Modulation and Within-Die Process Variation Effects
    Journal: lEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E97-A, No. 7, pp. 1461-1467
    Year: 2014
  6. Authors: T. Amaki, M. Hashimoto, Y. Mitsuyama, T. Onoye
    Title: A Worst-Case-Aware Design Methodology for Noise-Tolerant Oscillator-Based True Random Number Generator with Stochastic Behavior Modeling
    Journal: IEEE Transactions on Information Forensics and Security, Vol. 8, No. 8, pp. 1331-1342
    Year: 2013
  7. Authors: T. Kameda, H. Konoura, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, M. Hashimoto
    Title: Field Slack Assessment for Predictive Fault Avoidance on Coarse-Grained Reconfigurable Devices
    Journal: IEICE Transactions on Information and Systems, Vol. E96-D, No. 8, pp. 1624-1631
    Year: 2013
  8. Authors: D. Alnajjar, Y. Mitsuyama, M. Hashimoto, T. Onoye
    Title: Pvt-Induced Timing Error Detection Through Replica Circuits and Time Redundancy in Reconfigurable Devices
    Journal: IEICE Electronics Express (ELEX), Vol. 10, No. 5
    Year: 2013
  9. Authors: R. Harada, Y. Mitsuyama, M. Hashimoto, T. Onoye
    Title: Impact of NBTI-Induced Pulse-Width Modulation on Set Pulse-Width Measurement
    Journal:  IEEE Transactions on Nuclear Science
    Year: 2013
  10. Authors: D. Alnajjar, H. Konoura, Y. Ko, Y. Mitsuyama, M. Hashimoto, T. Onoye
    Title: Implementing Flexible Reliability in a Coarse-grained Reconfigurable Architecture
    Journal:  IEEE Transactions on VLSI Systems
    Year: 2012
  11. Authors: H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
    Title: Adaptive Performance Compensation with In-Situ Timing Error Predictive Sensors for Subthreshold Circuits
    Journal: IEEE Transactions on VLSI Systems, Vol. 20, No. 2, pp. 333-343
    Year: 2012
  12. Authors: H. Konoura, Y. Mitsuyama, M. Hashimoto, T. Onoye
    Title: Stress Probability Computation for Estimating NBTI-Induced Delay Degradation
    Journal: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E94-A, No. 12, pp. 2545-2553
    Year: 2011
  13. Authors: H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
    Title: Neutron-Induced Soft Errors and Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM
    Journal: IEEE Transactions on Nuclear Science, Vol. 58, No. 4, pp. 2097-2102
    Year: 2011
  14. Authors: R. Harada, Y. Mitsuyama, M. Hashimoto, T. Onoye
    Title: Measurement Circuits for Acquiring Set Pulse Width Distribution with Sub-Fo1-Inverter-Delay Resolution
    Journal: lEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E93-A, No. 12, pp. 2417-2423
    Year: 2010
  15. Authors: H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
    Title: Transistor Variability Modeling and its Validation With Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits
    Journal: lEEE Transactions on VLSl Systems, Vol. 18, No. 7, pp. 1118-1129
    Year: 2010
  16. Authors: H. Fuketa, M. Hashimoto, Y. Mitsuyama, T.Onoye
    Title: Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction
    Journal: IEICE Trans on Fundamentals of Electronics, Communications and Computer Science, Vol. E92-A, No. 12, pp. 3094-3102
    Year: 2009
  17. Authors: K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
    Title: An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability
    Journal: IEICE Transactions on Electronics, Vol. E92-C, No. 2, pp. 281-285
    Year: 2009
  18. Authors: Y. Mitsuyama, K. Takahashi, R. Imai, M. Hashimoto, T. Onoye, I. Shirakawa
    Title: Area-Efficient Reconfigurable Architecture for Media Processing
    Journal: IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E91-A, No. 12, pp. 3651-3662
    Year: 2008
  19. Authors: Y. Mitsuyama, M. Kimura, T. Onoye, I. Shirakawa
    Title: Architecture of IEEE802.11i Cipher Algorithms for Embedded Systems
    Journal: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E88-A, No. 4, pp. 899-906
    Year: 2005
  20. Authors: Z. Andales, Y. Mitsuyama, T. Onoye, I. Shirakawa
    Title: A Novel Dynamically Reconfigurable Hardware-based Cipher
    Journal: 情報処理学会論文誌, Vol. 42, No. 4, pp. 958-966
    Year: 2001
Awards
  1. IEEE CASS Shikoku Chapter Best Paper Award, IEEE CASS Shikoku Chapter, 2014
  2. Workshop on Synthesis And System Integration of Mixed In- formation technologies (SASIMI 2007) Outstanding Paper Award, In cooperation with IEEE, IEICE, IPSJ, and STARC, 2007
  3. IEEE Kansai Section Gold Award, IEEE Kansai Section, 2005
  4. International Symposium of Consumer Electronics (ISCE 2004) Best Paper Award, IEEE Consumer Electronics Society, 2004
Grants-in-Aid for Scientific Research from the Japanese government
  1. Project title: Performance-scalable reconfigurable system based on tightly-coupled reconfigurable devices
    Category: Grant-in-Aid for Young Scientists(B)
    Project number: 25730032
    Project period: 2013/04-2016/03
    Total budget amount: 3,510,000 yen
    Keywords: 

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Social activities

Committee roles
  1. International Conference on Field-Programmable Technology (ICFPT2018), Finance Chair, IEEE, 2016
  2. Transactions on Fundamentals, Special Section on "VLSI Design and CAD Algorithm", Guest Editor, IEICE, 2016-2017
  3. Transactions on Fundamentals (Japanese Edition), Director, IEICE, 2016
  4. Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2016), Registration Chair, IEEE, 2015-2016
  5. International Symposium on Communications and Information Technologies (ISCIT 2015), Program Committee, Track Co-Chair, IEEE, 2015-2015
  6. The Second International Symposium on Computing and Networking, Program Committee Member, IEICE, 2014-2014
  7. 2014 International Conference on Field-Programmable Technology (ICFPT2014), Program Committee Member, IEEE, 2014-2014
  8. The First International Symposium on Computing and Networking, Program Committee Member, IEICE, 2013-2013
  9. 2013 International Conference on Field-Programmable Technology (ICFPT2013), Program Committee Member, IEEE, 2013-2013

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