Faculty Members

tachibana-masayoshi-1.jpg

Professor
TACHIBANA, Masayoshi

  • Year of birth: 1959
  • Gender: Male
  • Affiliation:
    - School of Systems Engineering
    - Electronic and Photonic Systems Engineering Course, Department of Engineering, Graduate School of Enginering
Areas of specialization
Laboratory/research office Circuit Design Research Laboratory
Our laboratory studies the architecture of and design methodology for electronic circuits, in particular the analog part of analog mixed-signal (AMS) large scale integration (LSI). At present the main target of our research is the development of a Built-In Self Test (BIST) system for AMS LSI.
Current reseach topics
Educational background 1981: Bachelor
Professional background


Licenses
Academic societies

You can see the continuation of the table with a side swipe.

Courses

* Courses provided in English are shown with (E) mark

Undergraduate school
  • Analog Circuitry
  • Introduction to Computer Engineering
  • Circuit Theory: Network Analysis
  • Information Science 1
  • Experiments of Electronic and Photonic 2
  • Career Planning 2
  • Experiments in System Engineering
  • Graduation Thesis
Graduate school
  • Seminar 1
  • Seminar 2
  • Advanced Seminar 1
  • Advanced Seminar 2
  • Individual Work for Graduate
  • Design of Integrated Circuits

You can see the continuation of the table with a side swipe.

Research activities

Research papers
  1. Authors: Masayoshi Tachibana, Wilml San-Um
    Title: A simple current-reversible chaotic jerk circuit using inherent tanh(x) of an opamp
    Journal: IEICE Electronics Express, Vol. 14, No. 17, pp. 1-7
    Year: 2017
  2. Authors: TACHIBANA Masayoshi, Yuan Jun
    Title: A resistance matching based self-testable current-mode R-2R digital-to-analog converter
    Journal: IEICE Electronics Express, Vol. 10, No. 23, pp. 1-7, IEICE
    Year: 2013
  3. Authors: TACHIBANA Masayoshi, Jun Yan
    Title: A common-mode BIST technique for fully-differential sample-and-hold circuits
    Journal: IEICE Electronics Express, Vol. 9, No. 13, pp. 1128-1134, IEICE
    Year: 2012
  4. Authors: Tachibana Masayoshi, Wimol San-Um
    Title: A Low-Cost High-Speed Pluse Response Based Built-In self Test for Analog Integrated Circuits
    Journal: ECTI Trans. On Electrical Eng.,Electronics, and Communications
    Year: 2010
  5. Authors: Tachibana Masayoshi, Wimol San-Um
    Title: An On-Chip Analog Mixed-Signal Testing Compliant with IEEE 1149.4 Standard Using Fault Signature Characterization Technique
    Journal: ECTI Trans. On Electrical Eng.,Electronics, and Communications
    Year: 2010
  6. Authors: Wimol San-UM, Masayoshi Tachibana
    Title: A Fault Signature Characterization Based Analog Circuit Testing and the Extension of IEEE 1149.4 Standard
    Journal: IEICE Transactions on Information and Systems, Vol. E93-D, No. 1
    Year: 2010
  7. Authors: Wimol San-UM, Masayoshi Tachibana
    Title: A Impulse Signal Generation and Measurement Technique for Cost-Effective Built-In Self Test in Analog Mixed-Singal Systems
    Journal: Proceedings of the IEEE International Midwest Symposium on Circuit and Systems
    Year: 2009
  8. Authors: Wimol San-UM, Masayoshi Tachibana
    Title: A Compact on-Chip Testing Scheme for Analog-Mixed Signal System Using Two-Step AC and DC Fault Signature Characterizations
    Journal: Proceedings of the 15th Workshop on Synthesis and System Integration of Mixed Technologies, pp. 428-443
    Year: 2009
  9. Authors: M.Tachibana
    Title: Optical Micro Cell System: Smart Optical Wireless Access Data-Communication for Moving-User Terminals
    Journal: Japanese Journal of Applied Physics, Vol. 45, No. 8B, pp. 6762-6766
    Year: 2006
  10. Authors: Ampornrat Posri, Masayoshi Tachibana
    Title: Design of Transmitting and Recieving Section of Optical Wireless Access using PLL
    Journal: IQEC and CLEO-PR 2005, Vol. CThC3-P31, pp. 1410-1411
    Year: 2005
  11. Authors: M.Tachibana
    Title: Syntjesize Pass Transistor Logic Gate by Using Free BinaryDecision Diagram
    Journal: IEEE ASIC Conf., pp. 201-205
    Year: 1997
  12. Authors: M.Tachibana
    Title: Heuristic Algorithms for FBDD node Minimization with Application to Pass-Transistor-Logic and DCVS Synthesis
    Journal: SASIMI'96, pp. 96-101
    Year: 1996
  13. Authors: M.Tachibana, S.Kurosawa, R.Nojima, N.Kojima, M.Yamada, T.Mitsuhashi, N.Goto
    Title: Power and Area Minimization by Reorganizing CMOS Complex-Gates;
    Journal: IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, pp. 312-320
    Year: 1996
Grants-in-Aid for Scientific Research from the Japanese government
  1. Project title: Design of dependable Analog Mixed signal LSI with intermittent operatable BIST system
    Category: Grant-in-Aid for Scientific Research(C)
    Project number: 26330070
    Project period: 2014/04-2017/03
    Total budget amount: 4,680,000 yen
    Keywords: 
  2. Project title: Design of dependable Analog Mixed-Signal LSI with intermittent operation of fault detection system
    Category: Grant-in-Aid for Scientific Research(C)
    Project number: 23500067
    Project period: 2011/04-2014/03
    Total budget amount: 4,420,000 yen
    Keywords: 

You can see the continuation of the table with a side swipe.

Social activities

You can see the continuation of the table with a side swipe.