Research papers |
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Authors: Tang Xiaobin, Masayoshi Tachibana
Title: BIST Scheme for Dynamic Comparators
Journal: electronics, MDPI
Year: 2022
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Authors: Masayoshi Tachibana, Tang Xiaobin
Title: A BIST Scheme for Bootstrapped Switches
Journal: electronics, Vol. 10, MDPI
Year: 2021
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Authors: Wannaboon Chatchai, Masayoshi Tachibana, San-Um Wimol
Title: A 0.18-μm CMOS high-data-rate true random bit generator through ΔΣ modulation of chaotic jerk circuit signals
Journal: Chaos: An Interdisciplinary Journal of Nonlinear Science, American Institute of Physics
Year: 2018
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Authors: Chatchai Wannaboon, Nattagit Jiteurtragool, Wimol San-um, Masayoshi Tachibana
Title: Phase difference analysis technique for parametric faults BIST in CMOS analog circuits
Journal: IEICE Electronics Express, Vol. 15, No. 9, IEICE
Year: 2018
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Authors: Nattagit Jiteurtragool, Masayoshi Tachibana, Wiml San-Um
Title: Robustification of a One-Dimensional Generic Sigmoidal Chaotic Map with Application of True Random Bit Generation
Journal: Entropy , Vol. 20, No. 2, MDPI
Year: 2018
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Authors: Masayoshi Tachibana, Wilml San-Um
Title: A simple current-reversible chaotic jerk circuit using inherent tanh(x) of an opamp
Journal: IEICE Electronics Express, Vol. 14, No. 17, pp. 1-7
Year: 2017
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Authors: TACHIBANA Masayoshi, Yuan Jun
Title: A resistance matching based self-testable current-mode R-2R digital-to-analog converter
Journal: IEICE Electronics Express, Vol. 10, No. 23, pp. 1-7, IEICE
Year: 2013
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Authors: TACHIBANA Masayoshi, Jun Yan
Title: A common-mode BIST technique for fully-differential sample-and-hold circuits
Journal: IEICE Electronics Express, Vol. 9, No. 13, pp. 1128-1134, IEICE
Year: 2012
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Authors: Tachibana Masayoshi, Wimol San-Um
Title: A Low-Cost High-Speed Pluse Response Based Built-In self Test for Analog Integrated Circuits
Journal: ECTI Trans. On Electrical Eng.,Electronics, and Communications
Year: 2010
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Authors: Tachibana Masayoshi, Wimol San-Um
Title: An On-Chip Analog Mixed-Signal Testing Compliant with IEEE 1149.4 Standard Using Fault Signature Characterization Technique
Journal: ECTI Trans. On Electrical Eng.,Electronics, and Communications
Year: 2010
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Authors: Wimol San-UM, Masayoshi Tachibana
Title: A Fault Signature Characterization Based Analog Circuit Testing and the Extension of IEEE 1149.4 Standard
Journal: IEICE Transactions on Information and Systems, Vol. E93-D, No. 1
Year: 2010
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Authors: Wimol San-UM, Masayoshi Tachibana
Title: A Impulse Signal Generation and Measurement Technique for Cost-Effective Built-In Self Test in Analog Mixed-Singal Systems
Journal: Proceedings of the IEEE International Midwest Symposium on Circuit and Systems
Year: 2009
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Authors: Wimol San-UM, Masayoshi Tachibana
Title: A Compact on-Chip Testing Scheme for Analog-Mixed Signal System Using Two-Step AC and DC Fault Signature Characterizations
Journal: Proceedings of the 15th Workshop on Synthesis and System Integration of Mixed Technologies, pp. 428-443
Year: 2009
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Authors: M.Tachibana
Title: Optical Micro Cell System: Smart Optical Wireless Access Data-Communication for Moving-User Terminals
Journal: Japanese Journal of Applied Physics, Vol. 45, No. 8B, pp. 6762-6766
Year: 2006
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Authors: Ampornrat Posri, Masayoshi Tachibana
Title: Design of Transmitting and Recieving Section of Optical Wireless Access using PLL
Journal: IQEC and CLEO-PR 2005, Vol. CThC3-P31, pp. 1410-1411
Year: 2005
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Authors: M.Tachibana
Title: Syntjesize Pass Transistor Logic Gate by Using Free BinaryDecision Diagram
Journal: IEEE ASIC Conf., pp. 201-205
Year: 1997
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Authors: M.Tachibana
Title: Heuristic Algorithms for FBDD node Minimization with Application to Pass-Transistor-Logic and DCVS Synthesis
Journal: SASIMI'96, pp. 96-101
Year: 1996
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Authors: M.Tachibana, S.Kurosawa, R.Nojima, N.Kojima, M.Yamada, T.Mitsuhashi, N.Goto
Title: Power and Area Minimization by Reorganizing CMOS Complex-Gates;
Journal: IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, pp. 312-320
Year: 1996
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